Manufactured semiconductor chips may have defects. Those defective chips are tested and diagnosed by identifying the location and nature of the defects. Using a fault simulation technique, the defects are modeled as faults to determine which fault best matches or approximates the failing measures from the defects. Simulated faults are generally assigned a score to indicate how well the effects of the faults correlate to miscomparing measures detected by a tester. The best scoring fault is selected as the best model of the defect. The higher the score is, the better the fault models not only the location but also the nature of the defect. However, it is not practical to model all defects as faults.
Fault models include the stuck or stuck-at-fault model. The stuck-at-fault model models a faulted pin in a design that always produces a logic zero (for a stuck-at-zero fault) or a logic one (for a stuck-at-one fault). In order to detect the presence of a defect in the design that acts like a stuck-at-fault, the value at the faulted pin in the defective (stuck-at) state must be different from the value that should appear on that pin during the test. For instance, if the pin is expected to be at a one value in a specific state, then the stuck-at-zero fault models the difference on that pin in that state, whereas the stuck-at-one fault does not model the difference. Furthermore, the difference must be propagated to a point in the circuit at which the fault is measured. Typically, in the case of a fan-out net, a net with a single driver pin and multiple receiver pins, a stuck fault model consists of stuck faults on the driver pin of the net and stuck faults on the receiver pins on the net. Because there are no pins on internal sections of a fan-out net, the stuck fault does not model a defect on a net that feeds multiple receivers where the defective part of the net feeds only a subset of the receivers. Conventional diagnostics cannot achieve a high score with stuck fault models for such a defect that does not match a single logical pin stuck at either zero or one.
There are two approaches to resolve this problem. The first approach is to create a fan-out subnet fault model based on the logical design. In this approach, a fault is defined for each subset of fan-out receivers for each fan-out net. These faults are simulated, and the fan-out fault that best matches the values measured on a defective chip is used to model the defect in a subnet that feeds the subset of that net's fan-out receivers.
The fan-out subnet fault model is limited in that the number of faults to be modeled and simulated is impractical for a typical chip design. For instance, for a single net that has eight receivers, there are 28−1 or 255 combinations of receivers. Therefore, the total of 255 faults needs to be modeled. A typical circuit design has millions of nets, and it is not uncommon for some of these nets to fan out to hundreds of receivers. As the number of subnets and receivers increases, the number of subnet faults that need to be modeled and simulated grows exponentially. The number of faults becomes too large for practical modeling and simulation of modern chip designs.
The second approach is to analyze a physical circuit design to determine a set of receivers that a specific subnet feeds. Subnet faults are created only for those sets of receivers fed by a common subnet. This reduces the number of modeled faults. The modeled faults are simulated to determine the fault that best models the defect.
This approach is, however, limited in that it requires a physical circuit design and a methodology to map the physical circuit design to the nets and pins in a fault simulation model. When chips are manufactured, the mapping information between the physical design and the nets and pins in the fault simulation model may be lost or become unavailable. Even if the mapping information is available, it may be too expensive to recreate.
The various embodiments described herein enable identification of a subnet defect by compositing two or more faults without modeling or simulating any subnet faults respectively, thus overcomes the above-identified limitations.